Universal Remote Control R7 - SPECS SHEET Manual do Utilizador Página 31
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Data Sheet ADP5585
Rev. C | Page 31 of 40
RESET1_EVENT_B Register 0x2A
Table 50. RESET1_EVENT_B Bit Descriptions
Bit(s) Bit Name Access Description
7 RESET1_EVENT_B_LEVEL Read/write Defines which level the second reset event should be to generate the RESET1
signal. Refer to Table 49.
6 to 0 RESET1_EVENT_B[6:0] Read/write Defines an event that can be used to generate the RESET1 signal. Refer to Table 11.
RESET1_EVENT_C Register 0x2B
Table 51. RESET1_EVENT_C Bit Descriptions
Bit(s) Bit Name Access Description
7 RESET1_EVENT_C_LEVEL Read/write Defines which level the second reset event should be to generate the RESET1
signal. Refer to Table 49.
6 to 0
RESET1_EVENT_C[6:0]
Read/write
Defines an event that can be used to generate the RESET1 signal. Refer to Table 11.
RESET2_EVENT_A Register 0x2C
Table 52. RESET2_EVENT_A Bit Descriptions
Bit(s) Bit Name Access Description
7 RESET2_EVENT_A_LEVEL Read/write Defines which level the first reset event should be to generate the RESET2 signal.
For key events, use the following settings:
0 = not applicable; releases not used for reset generation.
1 = press is used as reset event.
For GPIs and logic outputs configured for FIFO updates, use the following settings:
0 = inactive event used as reset condition.
1 = active event used as reset condition.
6 to 0 RESET2_EVENT_A[6:0] Read/write Defines an event that can be used to generate the RESET2 signal. Up to two events
can be defined for generating the RESET2 signal, using RESET2_EVENT_A[6:0], and
RESET2_EVENT_B[6:0]. If one of the registers is 0, that register is not used for reset
generation. All reset events must be detected at the same time to trigger the reset.
RESET2_EVENT_B Register 0x2D
Table 53. RESET2_EVENT_B Bit Descriptions
Bit(s) Bit Name Access Description
7 RESET2_EVENT_B_LEVEL Read/write Defines which level the second reset event should be to generate the RESET2
signal. Refer to Table 52.
6 to 0 RESET2_EVENT_B[6:0] Read/write Defines an event that can be used to generate the RESET2 signal. Refer to Table 11.
RESET_CFG Register 0x2E
Table 54. RESET_CFG Bit Descriptions
Bit(s) Bit Name Access Description
7 RESET2_POL Read/write Sets the polarity of RESET2.
0 = RESET2 is active low.
1 = RESET2 is active high.
6
RESET1_POL
Read/write
Sets the polarity of RESET1.
0 = RESET1 is active low.
1 = RESET1 is active high.
5
RST
_PASSTHRU_EN
Read/write
Allows the
RST
pin to override (OR with) the RESET1signal. This function not
applicable to RESET2.
- ADP5585 1
- TABLE OF CONTENTS 2
- SPECIFICATIONS 3
- ABSOLUTE MAXIMUM RATINGS 5
- THEORY OF OPERATION 7
- DEVICE ENABLE 8
- DEVICE OVERVIEW 8
- EVENT FIFO 9
- KEY SCAN CONTROL 9
- ADP5585 Data Sheet 10
- 09841-012 11
- 09841-013 11
- Data Sheet ADP5585 13
- 09841-020 14
- Interrupts 14
- REGISTER INTERFACE 15
- Rev. C 16
- REGISTER MAP 17
- ID Register 0x00 19
- INT_STATUS Register 0x01 19
- Status Register 0x02 19
- FIFO_1 Register 0x03 19
- FIFO_2 Register 0x04 20
- FIFO_3 Register 0x05 20
- FIFO_4 Register 0x06 20
- Rev. C 21
- Rev. C 22
- GPI_STATUS_A Register 0x15 23
- GPI_STATUS_B Register 0x16 23
- RPULL_CONFIG_A Register 0x17 24
- RPULL_CONFIG_B Register 0x18 24
- RPULL_CONFIG_C Register 0x19 25
- RPULL_CONFIG_D Register 0x1A 25
- GPI_EVENT_EN_A Register 0x1D 26
- GPI_EVENT_EN_B Register 0x1E 26
- DEBOUNCE_DIS_A Register 0x21 28
- DEBOUNCE_DIS_B Register 0x22 28
- GPO_DATA_OUT_A Register 0x23 28
- GPO_DATA_OUT_B Register 0x24 29
- GPO_OUT_MODE_A Register 0x25 29
- GPO_OUT_MODE_B Register 0x26 29
- RESET1_EVENT_A Register 0x29 30
- RESET1_EVENT_B Register 0x2A 31
- RESET1_EVENT_C Register 0x2B 31
- RESET2_EVENT_A Register 0x2C 31
- RESET_CFG Register 0x2E 31
- PWM_OFFT_LOW Register 0x2F 32
- PWM_OFFT_HIGH Register 0x30 32
- PWM_ONT_LOW Register 0x31 32
- PWM_ONT_HIGH Register 0x32 32
- PWM_CFG Register 0x33 32
- LOGIC_CFG Register 0x34 33
- LOGIC_FF_CFG Register 0x35 33
- POLL_TIME_CFG Register 0x37 34
- PIN_CONFIG_A Register 0x38 34
- PIN_CONFIG_B Register 0x39 34
- PIN_CONFIG_C Register 0x3A 34
- GENERAL_CFG Register 0x3B 35
- INT_EN Register 0x3C 35
- APPLICATIONS DIAGRAM 36
- OUTLINE DIMENSIONS 37
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